The present invention relates to circuits and methods for controlling the Power On Reset (POR) sequence in an Integrated Circuit (IC), and more particularly, circuits and methods for controlling an external test POR signal used for testing the IC.
Programmable devices contain millions of Static Random Access Memory (SRAM) cells holding the configuration of the programmable device. During power up, all the SRAM cells need to be reset into a known state. The reset of the SRAM cells is typically performed by a POR signal generated by a POR circuit. The POR signal is active during the POR phase of the initialization stage of the IC, and before the configuration stage where the user information is loaded into the SRAM cells. The POR signal is also used to configure the I/O circuitry of the IC, as well as to eliminate conflicts in the IC that may draw unsustainable, or even damaging, current from the power supply.
Some devices include a test POR input pin used for testing how changes in the power supply affect the performance of the IC. Typically, the POR signal is generated during power up, or when the power supply goes below a certain threshold voltage that forces the IC to go thorough a new POR sequence. In order to test the response of the IC to fluctuations in power supply, the test POR input overrides the POR signal to avoid the initialization of a new POR sequence when the voltage level falls below the threshold voltage.
While the test POR input helps in the testing and debugging of the IC, the test POR signal can also be used to read the contents of the SRAM cells by lowering the power supply and using the test POR input to avoid resetting the device. This potentially enables the cloning of the IC by someone without the original configuration that uses the test POR input to read the SRAM cells. Once the configuration of the IC is obtained, another device can be programmed with the same configuration to clone the original device.
It is in this context that embodiments of the invention arise.